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| www..com CHIP-CEIVER - Single Chip FM Transceiver TM 902 - 928 MHz NT2903 FEATURES * * * * * * * * * * Direct-Conversion, Zero-IF, Architecture Wide Bandwidth FM Transceiver Suitable for FM/FSK Modulation Dual, On-Chip PLL Synthesizers/VCOs 3-wire serial interface System Noise Figure 4.7 dB (typ.)* 2.7 - 3.3V Operation / Standby Mode No Tune "Tankless" Detector RF Output +1.5 dBm Low Cost, Thin-Quad Flat Package, (TQFP-48) APPLICATIONS Analog/Digital "900 MHz" Cordless Phones .com Telemetry/Data Radios Wireless Local Area Networks (WLAN) ISM Band (900 MHz) Wireless Products DataShee GENERAL DESCRIPTION The NT2903 CHIP-CEIVERTM is a complete, single chip, FM transceiver solution, which will operate in any 24 MHz band from 800-1000 MHz, including the Industrial Scientific Medical (ISM) band (902-928 MHz). Utilizing a unique direct-conversion, zero-intermediate frequency (zero-IF) receiver architecture, the NT2903 CHIP-CEIVERTM provides radio designers with a "simple" RF path design solution. The device is fabricated as a monolithic, BiCMOS, integrated circuit. The device's receiver section provides all of the required RF synthesis, filtering, gain control, AFC, and demodulation functions. The transmitter section contains a directly modulated VCO and RF power amplifier (PA). Internal, dual, high-performance phase locked loop (PLL) synthesizers/VCOs allow full-duplex Tx/Rx operation over the entire RF tuning range. Tuning, power management, and gain control functions are accomplished via a 3-wire serial interface. Information furnished by NUMA Technologies is believed to be accurate and reliable. However, no responsibility is assumed by NUMA Technologies for its use; nor for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of NUMA Technologies. 5551 Ridgewood Drive, Suite 303 Naples Florida 34108 Phone: (941) 591-8008 FAX: (941) 591-8704 e-mail numatech@peganet.com 4Q/99REV(A) NUMA Technologies .com * Refer to Applications section for additional details DataSheet 4 U .com www..com PRODUCT DESCRIPTION The BiCMOS construction of the NT2903 CHIP-CEIVERTM provides a high level of integration, with high performance operation and low power consumption. The CHIPCEIVERTM operates over an industrial temperature range of -20C to +65C and over the supply voltage of +2.7 V to +3.3 V. The device is available in an industry standard plastic package as a thin-quad flat package (TQFP). FUNCTIONAL DESCRIPTION A functional block diagram of the NT2903 CHIP-CEIVERTM is shown in Fig.(1). The receive section of the device consists of several major function blocks, including a switchable RF input attenuator, quadrature mixer (down-conversion), differential to singleended buffers, PLL synthesizer / voltage controlled oscillator (VCO), I/Q low-pass filters, variable gain amplifiers (VGA), DC offset correction circuitry, quadrature mixer (upconversion), zero-crossing detector, Period-to-Digital converter (P/D), Linearization ROM, and a Digital-to-Analog converter (DAC). Additionally, the device contains a reference crystal oscillator / automatic frequency control (AFC) circuitry. The transmit section of the device consists of a PLL synthesizer / directly modulated voltage controlled oscillator (VCO), and a RF power amplifier (PA). t4U.com BUF DataShee LPF1 (I) LPF2 (I) VGA .com RF IN PAD 0/-10dB 90 DC OFFSET CORRECTION DIV 90 SUM IF BPF ZERO X P/D 512 X 9 ROM BUF LPF1 (Q) LPF2 (Q) VGA DIV Rx PLL SYNTHESIZER/ VCO RF OUT (+1.5dBm) PA Tx PLL SYNTHESIZER/ VCO AUDIO/DATA INPUT REF OSC RSSI AFC 9 BIT DAC CLOCK DATA LE RSSI OUTPUT AFC OUTPUT AUDIO OUTPUT Figure (1), NT2903 CHIP-CEIVERTM - Functional Block Diagram The receiver section of the NT2903 CHIP-CEIVERTM utilizes a quadrature mixer in a directconversion, zero-intermediate frequency (zero-IF) approach. After quadrature downconversion and baseband filtering, a quadrature mixer up-converts the complex baseband signal to an intermediate frequency (IF) for digitization. Direct conversion, (zero-IF) has several advantages over super-heterodyne approaches. First, the problem of image is eliminated because the IF is zero. Second, the use of active, low pass, filters provide a high level of integration, while eliminating the need for external IF filters and IF transformers. The digital data from the P/D converter is fed to a "brick wall" filter, which limits excess receiver bandwidth, thereby improving receiver performance. .com 2 DataSheet 4 U .com www..com FUNCTIONAL DESCRIPTION - Cont. Receiver selectivity is accomplished using low pass filters (LPFs) in the I/Q complex baseband section. The device employs fully integrated, active filters for channel selectivity and receiver bandwidth control. The transmitter section of the NT2902 CHIP-CEIVERTM is comprised of a modulator circuit, a PLL synthesizer / VCO, and a RF power amplifier (PA) capable of providing +1.5 dBm into a 50 load. A description of each of the major function blocks follows: RF Input Attenuator Pad - A switchable 0/-10dB attenuator pad allows high signal level capability at the RF Input of the receiver. This pad is located prior to the quadrature mixer (down-conversion) and can be either manually controlled via the 3-wire interface, or automatically controlled via the AGC section of the device. Quadrature Mixer (down-conversion) - The quadrature mixer is a critical part of the CHIP-CEIVERTM zero intermediate-frequency (zero-IF) design. The main advantage of the quadrature mixer is its ability to translate the RF frequency directly to a zero-IF, thereby eliminating the image frequency. Consequently, the image filter between the external LNA and the RF input to the CHIP-CEIVERTM can be eliminated in most designs. The design requirements for the duplexer and RF bandpass filter may also be relaxed. In addition, the quadrature mixer achieves a lower overall noise figure by virtue of image frequency elimination. The balanced mixers in the quadrature mixer are designed to closely track .com each other in both amplitude and phase response. Additionally, the quadrature LO signal is generated by direct division of the receiver LO, thereby eliminating external phase shifting networks. Furthermore, for improved noise immunity, all internal RF signal paths are fully differential, thereby providing common mode noise rejection. The gain of the mixer can be adjusted by attenuating the baseband output. PLL Synthesizer (Receive) - The receive (Rx) on-chip PLL synthesizer with voltage controlled oscillator (VCO), is designed to provide a low phase noise, local oscillator (LO) drive for the quadrature, down-conversion RF mixer. The RxVCO operates in a balanced mode at 2x the Rx frequency (1.8 GHz). The 1.8 GHz VCO is immediately divided by 2 to 900 MHz, subsequently this signal is fed to a modulus prescaler (32/33) and then into the synthesizer which produces a 50 kHz signal. This feedback signal is compared at the phase detector with a reference signal (50 kHz), which is derived from the reference oscillator and reference divider. The 1.8 GHz divide by 2 also produces the quadrature LO drive (900 MHz) for the RF quadrature mixer. The Rx VCO center frequency is determined by an external tank circuit comprised of a printed, center-tapped, inductor. The tank circuit is connected to RVCO (41) and /RVCO (42) respectively. An external PLL loop filter network, connected to the RPLL pin (39), filters the VCO control voltage. This control voltage (KVCO 52 MHz/V @ 1.8GHz) is used to tune the tank frequency of the VCO via an internal, common-anode, varactor pair. The receive frequency for the CHIPCEIVERTM is programmed via a three (3) wire compatible, serial interface (Data, Clock, and Load Enable). .com 3 t4U.com DataShee DataSheet 4 U .com www..com FUNCTIONAL DESCRIPTION - Cont. Buffer Amplifiers - The buffer amplifiers provide differential to single-ended conversion of the baseband signal prior to the I/Q low-pass filters, which are referenced to an internally generated virtual ground. LPF1 (I/Q) - This first stage of the I/Q baseband low pass filter (LPF) section consists of active, Sallen-key type filters. These filters provide a combination of low noise figure and gain along with a wide dynamic input range. The purpose of these filters is to provide preliminary rejection of the out-of-band interfereres. The reduction of out-of-band interferer levels, reduce the dynamic range requirements for the following filter stages in LPF2. The -3dB corner frequency of these LPFs are set via external RC values. LPF2 (I/Q) - This second stage of the I/Q baseband low pass filter (LPF) section consists of active, transconductance (gm) type filters. Combined with LPF1, these filters provide the required channel selectivity by passing the entire desired frequency spectrum, while attenuating noise and adjacent channel interference (ACI), outside of the desired signal's bandwidth. DC Offset Correction - A proprietary DC offset correction circuit is used in the NT2903 to control DC offset voltages which can degrade receiver performance. The correction circuit operates automatically in a continuous mode. .com t4U.com DataShee Quadrature Mixer (up-conversion) - The quadrature up-conversion mixer forms yet another important part of the overall CHIP-CEIVERTM design. This quadrature mixer translates the filtered baseband signal from one frequency to another i.e. the zero-IF, complex, baseband spectrum is translated by the quadrature up-conversion mixer to a frequency centered about the LO mixer frequency. The resultant up-converted IF signal is low enough in frequency to provide adequate SNR at the output of the period-to-digital converter (P/D), yet high enough to satisfy signal sampling criterion. IF BPF - The intermediate frequency (IF), bandpass filter (BPF) after the quadrature upconversion mixer passes the lowest frequency signal components and rejects the third harmonic component of the up-conversion mixer's local oscillator (LO). The IF bandpass filter is comprised of cascaded, active, transconductance filters with Butterworth response characteristics. RSSI - The receive signal strength indication (RSSI) measurement circuitry incorporates a log amplifier and detector for the purpose of measuring the received RF carrier power level. The output is a DC voltage, which is linear over a 50dB dynamic range. The RSSI measurement range is from -116dBm to -66dBm with the RF input pad bypassed (0dB) and the quadrature mixer gain set to high. The RSSI conversion factor is -30mV/dB, with a voltage range of 1.8VDC. .com 4 DataSheet 4 U .com www..com FUNCTIONAL DESCRIPTION - Cont. AFC - Automatic Frequency Control of the receive local oscillator (LO) frequency is used to improve receiver performance. Without AFC, frequency offsets cause a reduction in SINAD due to filter distortion. A reduction in SINAD of 4-5dB is typical at a frequency offset of 20kHz. Additionally, due to the zero-IF architecture of the NT2903 AFC is used to reduce beat note levels. The AFC correction voltage, which is generated internally in the NT2903, is available as a DC voltage at the AFC (46) output pin. This correction voltage is typically used to bias an external varactor, which is parallel to the input load capacitor of the reference oscillator circuit. The AFC correction voltage is derived by double integration of the demodulated FM signal. The AFC attack time is governed by two factors; an external capacitor connected to the AFCC (47) pin and a loop damping resistor and capacitor at the output pin of the AFC (46) output pin. Comparator - A high speed BiCMOS comparator performs the basic function of a "Limiter" and is used to detect the intermediate frequency (IF) zero-crossing events. The "half-cycle" intervals of the IF are output from the comparator in the form of a pulse, which is subsequently measured by the Period-to-Digital (P/D) converter. Complimentary outputs from the comparator provide alternating "half-cycle" gating signals to the P/D converter. .com t4U.com DataShee Period-to-Digital (P/D) Converter - The quantizer used in the CHIP-CEIVERTM employs the NUMA Technologies' Period-to-Digital (P/D) converter as the digitizer. The basic principal of the P/D relies on it's ability to integrate and dump sequential half-cycle intervals of the IF signal with high resolution. The numerical output from the P/D is the form of 1/f or period of the intermediate frequency (IF) signal. The clock signal for the P/D is derived from the RxVCO oscillator. A functional block diagram of the P/D clock generation is shown in Fig. (2). UC Mixer LO Generation /16 "902.3 MHz" from RxVCO PLL Loop /11 /2 /18 P/D Clock 82.02 MHz UC Mixer LO 142.4 kHz Figure (2), P/D Converter Clock Generation - Functional Block Diagram .com 5 DataSheet 4 U .com www..com FUNCTIONAL DESCRIPTION - Cont. Linearization ROM - The information from the period-to-digital converter (P/D) is in the form of a period measurement (1/f) of each half cycle of the IF signal. Each data value from the P/D is used to address a pre-programmed value in the linearization ROM. In this manner, the linearization ROM is used as a look-up table which provides the required 1/p conversion to convert the period information of the P/D to frequency, in a linear fashion. The ROM maybe programmed with different numerical values, thereby providing different detector response characteristics, for use in either analog or digital modulation schemes. D/A Converter - The Digital-to-Analog (DAC) converter along with the output from the P/D converter form a "tankless discriminator". A digital-to-analog converter (DAC) provides a special transfer function, which is required to linearize the digital data "period" value from the P/D converter. The resultant analog signal is the recovered audio (demodulated FM). PLL Synthesizer (Transmit) - The transmit (Tx) on-chip PLL synthesizer with an onchip, voltage controlled oscillator (VCO), contains a dual-modulus prescaler (32/33) and employs a digital phase locked loop architecture. The transmit VCO operates at 900 MHz. The transmit PLL accepts modulation audio to provide a frequency modulated (FM) RF carrier. Utilizing a direct modulation approach, the modulation voltage is directly applied to the PLL loop filter. The VCO center frequency is determined by an external tank circuit comprised of two inductors connected to the TVCO (15) and /TVCO (16). An .com external PLL loop filter network, connected to the TPLL pin (13), filters the VCO control voltage. This control voltage (KVCO 26 MHz/V) is used to tune the tank frequency of the VCO via an internal, common-anode, varactor pair. The transmit frequency for the CHIPCEIVERTM is programmed via a three (3) wire compatible, serial interface (Data, Clock, and Load Enable). PA - The on-chip RF power amplifier is a differential gain stage. The power amplifier requires a combiner network as shown in the application circuit (Fig 3). The combiner network converts the amplifier's differential output (balanced 700) to a single-ended one, capable of delivering +1.5 dBm into a 50 load. Variable Receiver Gain - The gain of the receiver can be dynamically adjusted via the 3wire interface to maintain signal linearity before the demodulator. This enables the achievement of high values of SINAD for an analog FM link. An Automatic Gain Control (AGC) function is also available on chip. The gain can be manually adjusted in 3 locations by the following: 1. A 10dB RF pad before the Quadrature mixer (PAD in figure 1) 2. Four step baseband attentuators in the RF quadrature I and Q mixer load circuits giving nominal voltage conversion gains of 18, 8, -2, -13dB for each channel. 3. Three step baseband Variable Gain Amplifiers after the baseband I and Q low pass filters giving voltage gains of 40, 30, 20 and 10 dB. .com 6 t4U.com DataShee DataSheet 4 U .com www..com PIN CONFIGURATION Plastic Thin Quad Flat Package (TQFP-48 pin) PIN DESCRIPTIONS This section summarizes the pin descriptions of the NT2903 CHIP-CEIVERTM by pin name. t4U.com Pin Name LE Pin Number Description (1) Load Enable: This CMOS compatible input when HIGH .com allows data to be shifted into the internal shift register. Serial Data Input: This CMOS compatible input accepts data MSB first. Refer to page (13) for additional information on the programming format. Serial Clock: This CMOS compatible input shifts serial data into the internal 20-bit serial shift register, upon the rising edge of the clock signal. Digital ground: This is the ground pin for the internal CMOS digital circuitry, crystal oscillator, AFC, period-todigital (P/D) converter, ROM, and Digital-to-Analog converter (DAC). Oscillator Input: This CMOS input is the reference frequency input for both the Tx and Rx PLLs. When used with an external reference oscillator, the signal level should be within the range of 200-400mV peak. Additionally, this input can be used with the OSCO pin to form a Colpitts crystal oscillator. Figure (3) of the application circuit illustrates the use of the internal oscillator. DataShee DATA (2) CLK (3) VSS (4) OSCI (5) .com 7 DataSheet 4 U .com www..com PIN DESCRIPTIONS - Cont. OSCO (6) Oscillator Output: This CMOS compatible output is used in conjunction with OSCIN to form a Colpitts oscillator using an external, low cost, crystal (parallel-resonant). Digital power supply: This is the power supply pin for the internal CMOS digital circuitry, crystal oscillator, AFC, period-to-digital (P/D) converter, and Digital-to-Analog converter (DAC). This pin should be de-coupled to ground, as close to the pin as possible, with a high quality .1F ceramic capacitor. RF output power supply: This is the power supply pin for the internal power amplifier (PA) and transmit VCO prescaler. RF Amplifier Outputs: These are the differential outputs of the power amplifier which require a combiner network as shown in the application circuit (Fig 3). The output impedance of the power amplifier (PA) is 700 (differential). The combiner circuit, (Fig 3) allows the .com delivery of 1.5 dBm into a 50 load. RF output ground: This is the ground pin for the internal power amplifier (PA) and transmit TxVCO prescaler. Transmit VCO ground: This is the ground pin for the internal transmit voltage controlled oscillator and transmit PLL charge pump. This pin should be connected to an RF ground plane using through-hole vias. Transmit Voltage Controlled Oscillator: This pin connects to an external PLL loop filter. This filtered tuning voltage provides the tuning voltage for the internal varactor tuning diodes. The PLL loop dynamics are controlled by the loop filter component values. Transmitter modulation is accomplished by directly applying the modulating signal (Audio/Data) to the PLL loop, via an external coupling network. VDD (7) VDDO (8) RFO, \RFO t4U.com (9, 10) DataShee VSSO (11) VSST (12) TPLL (13) .com 8 DataSheet 4 U .com www..com PIN DESCRIPTIONS - Cont. VDDT1 VDDT2 (14,17) Transmit VCO power supply: These are the power supply pins for the internal transmit voltage controlled oscillator and transmit PLL charge pump. These pins should be decoupled to ground, as close to each pin as possible, with RF quality 100pF and 1.0nF ceramic capacitors. Transmit VCO Tank: These single-end outputs drive the external, balanced, VCO resonant tank circuit. The tank circuit generates the overall oscillation frequency for the TxVCO. Careful layout is required to prevent RF leakage to the RxVCO tank circuit and the associated receive input circuitry. Gain Control Capacitor: This pin connects to an external 100 nF capacitor connected to VSSA, which provides decoupling for the internal gain control circuitry. DC Offset RSSI: This pin is connected to an external 330 nF capacitor connected to VSSA, which removes residual DC offset from the RSSI measurement circuitry. .com TVCO /TVCO (15,16) GCC (18) DCR t4U.com (19) DataShee DCQ (20) DC Offset (Q): This pin is connected to an external 330 nF capacitor connected to VSSA, which removes residual DC offset from the baseband signal Q(t). DC Offset (I): This pin is connected to an external 330 nF capacitor connected to VSSA, which removes residual DC offset from the baseband signal I(t). Baseband In-phase (I) Filter: These pins connect to an external RC network which set the corner frequency of the first I/Q baseband, Sallen-key, filter stage. Baseband Filter Set: This pin connects to an external resistor, which sets the corner frequency of the transconductance (gm) baseband (I/Q) filter stages. Baseband Quadrature (Q) Filter: These pins connect to an external RC network which set the corner frequency of the first I/Q baseband, Sallen-key, filter stage. DCI (21) IFIL1,2,3 (23, 24, 22) BBSET (25) QFIL1,2,3 (27, 26, 28) .com 9 DataSheet 4 U .com www..com PIN DESCRIPTIONS - Cont. PFGND (29) Pre-Filter Ground: This pin connects to an external 100 nF capacitor connected to VSSA, which provides de-coupling for the internal pre-filter buffer ground nodes. Baseband and IF Filter power supply: This is the power supply pin for the I/Q filters, amplifiers, RSSI, up-conversion mixer, and IF filter. This pin should be de-coupled to ground, as close to the pin as possible, with a high quality .1F and 1nF ceramic capacitors. Baseband and IF Filter ground: This is the ground pin for the I/Q filters, amplifiers, RSSI, up-conversion mixer, and IF filter. RF Input power supply: This is the power supply pin for the internal RF Quadrature mixer. This pin should be decoupled to ground, as close to the pin as possible, with RF quality 100pF and 1.0nF ceramic capacitors. RF Input (balanced 100): This is the small signal .com RF differential inputs to the NT2903. An RF differential input signal is generated by an external phase splitter circuit and matching circuit, as shown in the applications circuit in (Fig 3). These inputs must be AC coupled to prevent damage to the input bias circuitry. RF Input ground: This is the ground pin for the internal RF Quadrature mixer. This pin should be connected to an RF ground plane using through-hole vias. Receive Signal Strength Indicator: This output pin provides a current output, into an external shunt resistor and capacitor (48k//10nF) connected to VSS, to develop a filtered voltage level, proportional to the receive RF signal strength. The output is linear over a 50 dB range with an output swing of 0.2 to 2.0 Vdc. The active range of the RSSI is from low signal strength, i.e. -116dBm to -66dBm (GCHIGH). VDDA (30) VSSA (31) VDDI (32) t4U.com \RFI RFI (33, 34) DataShee VSSI (35) RSSI (36) .com 10 DataSheet 4 U .com www..com PIN DESCRIPTIONS - Cont. SUBS* (37) Substrate: This pin is connected to the silicon substrate and should be connected to a "clean" ground plane. *This pin shall become a modulation input for utilization of the separate modulation varactor in future versions if required. VSSR (38) Receive VCO ground: This is the ground pin for the internal receive voltage controlled oscillator and receive PLL charge pump. This pin should be connected to an RF ground plane using through-hole vias. Receive Voltage Controlled Oscillator: This pin connects to an external PLL loop filter. This filtered tuning voltage provides the tuning voltage for the internal varactor tuning diodes. The PLL loop dynamics are controlled by the loop filter component values. Receive VCO power supply: These are the power supply pins for the internal receive voltage controlled oscillator and receive PLL charge pump. These pins should be de-coupled .com to ground, as close to each pin as possible, with RF quality 100pF and 1.0nF ceramic capacitors. Receive VCO Tank: These single-end outputs drive the external, balanced, RxVCO resonant tank circuit. The tank circuit generates the overall oscillation frequency for the RxVCO. The RxVCO tank frequency is 2X the desired Rx LO frequency, since the on-chip quadrature generation circuitry divides this LO signal by 2. The CHIP-CEIVERTM is a direct conversion, zero-IF receiver, therefore the quadrature LO frequency is the same as the receive frequency, (i.e. no IF offsets). Careful layout is required to prevent RF leakage to the TxVCO tank circuit and associated transmit circuitry. IF Filter: This pin connects to an external resistor, which sets the corner frequencies of the IF transconductance (gm) filter stages. AC Ground: This pin connects to an external 100 nF capacitor connected to VSSA, which provides de-coupling for the internal baseband and IF filter ground nodes. RPLL (39) t4U.com VDDR1 VDDR2 (40,43) DataShee RVCO /RVCO (41,42) IFSET (44) ACGND (45) .com 11 DataSheet 4 U .com www..com PIN DESCRIPTIONS - Cont. AFC (46) Automatic Frequency Control: This output pin connects to an external filter, which provides the DC control voltage for the automatic frequency control (AFC) circuitry. The component values of the filter establish the AFC loop delay or "attack time". Automatic Frequency Control Capacitor: This pin connects to external de-coupling capacitors (150 nF), which provide filtering for an internal reference voltage. Audio Output: In the Analog mode, this output pin provides the recovered, demodulated audio signal. The audio signal level is 200 mVrms. (typ). In the Digital mode, this CMOS compatible output provides serial data from the internal data slicer. AFCC (47) AUDO (48) t4U.com DataShee .com .com 12 DataSheet 4 U .com www..com Tx/Rx PLL PROGRAMMING and SERIAL INTERFACE The Tx/Rx VCO divide ratios are controlled by a standard 3-wire bus comprised of Clock, Load Enable, and Data inputs. The programming word contains 20 bits, the first two bits select the programming of the receive VCO frequency, the transmit VCO frequency, the reference frequency or the device operational modes. The remaining bits contain the data to be programmed. Clock Data 20 19 18 17 16 ............... 6 5 4 3 2 1 The above diagram shows the programming format. t4U.com Data is clocked into the internal shift registers on the positive edge of the CLOCK (3) pin, while Load Enable (1) pin is held HIGH. Data is loaded from the shift registers into the data registers on the negative edge of the Load Enable (LE). This load is NOT .com synchronized with the programmable divider, i.e. the load is controlled directly by the negative falling edge of the Load Enable. DataShee Data Register Contents Reference Frequency Select Bit 1 (last bit loaded) Bit 2 Bit 3 Ref(1) LSB Bit 4 Ref(2) Bit 5 Ref(3) Bit 6 Ref(4) Bit 7 Ref(5) Bit 8 Ref(6) Bit 9 Ref(7) Bit 10 Ref(8) Bit 11 Ref(9) Bit 12 Ref(10) MSB Load control bit 1 = (0) Load control bit 2 = (0) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Reference divide register (count 1 to 1024) Internal Reference Frequency = (Reference Oscillator Frequency) / Ref(10:1) .com 13 DataSheet 4 U .com www..com PLL Data Register Contents Cont. Receive VCO Frequency Select Bit 1 (last bit loaded) Bit 2 Bit 3 LSB VCO frequency Bit 4 VCO frequency Bit 5 VCO frequency Bit 6 VCO frequency Bit 7 MSB VCO frequency Bit 8 LSB VCO frequency Bit 9 VCO frequency Bit 10 VCO frequency Bit 11 VCO frequency Bit 12 VCO frequency Bit 13 VCO frequency Bit 14 VCO frequency Bit 15 VCO frequency Bit 16 VCO frequency Bit 17 MSB VCO frequency Bit 18 Bit 19 Bit 20 Load control bit 1 = (1) Load control bit 2 = (0) A Ra(1) A Ra(2) A Ra(3) A Ra(4) A Ra(5) M* Rm(1) M Rm(2) M Rm(3) M Rm(4) M Rm(5) M Rm(6) M Rm(7) M Rm(8) M Rm(9) M Rm(10) .com t4U.com A register A register A register A register A register M register M register M register M register M register M register M register M register M register M register DataShee Rx VCO Trim bit 1 Rx VCO Trim bit 2 Rx VCO Trim bit 3 *Future version to provide an additional M counter bit. RxVCO Frequency = Internal Reference Frequency x (32 x M(10:1) + A(5:1)) Rx VCO Trim Bits 2 0 0 1 1 0 0 1 1 3 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 Trim Number 0 - Minimum C 1 2 3 4 5 6 7 - Maximum C .com 14 DataSheet 4 U .com www..com PLL Data Register Contents - Cont. Transmit VCO Frequency Select Bit 1 (last bit loaded) Bit 2 Bit 3 LSB VCO frequency Bit 4 VCO frequency Bit 5 VCO frequency Bit 6 VCO frequency Bit 7 MSB VCO frequency Bit 8 LSB VCO frequency Bit 9 VCO frequency Bit 10 VCO frequency Bit 11 VCO frequency Bit 12 VCO frequency Bit 13 VCO frequency Bit 14 VCO frequency Bit 15 VCO frequency Bit 16 VCO frequency Bit 17 MSB VCO frequency Load control bit 1 = (0) Load control bit 2 = (1) A Ta(1) A Ta(2) A Ta(3) A Ta(4) A Ta(5) M Tm(1) M Tm(2) M Tm(3) M Tm(4) M Tm(5) M Tm(6) M Tm(7) M Tm(8) M Tm(9) M Tm(10) t4U.com A register A register A register A register A register M register M register M register M register M register M register M register M register M register M register DataShee Future version to provide an additional M counter bit. .com Bit 18 Bit 19 Bit 20 Tx VCO Trim bit 1 Tx VCO Trim bit 2 Tx VCO Trim bit 3 TxVCO Frequency = Internal Reference Frequency x (32 x M(10:1) + A(5:1)) Tx VCO Trim Bits 2 0 0 1 1 0 0 1 1 3 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 Trim Number 0 - Minimum C 1 2 3 4 5 6 7 - Maximum C .com 15 DataSheet 4 U .com www..com PLL Data Register Contents - Cont. Mode and Test Mode select Bit 1 Load Control Bit 1 (Last bit loaded) Bit 2 Load Control Bit 2 For Mode and Test Mode select (BIT 2 = 1, Bit 1 = 1,) Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Auto Gain Control 0 = Off Receive Section 0 = Off Transmit Section 0 = Off Receive Charge Pump Current 0 = 0.2mA Transmit Charge Pump Current 0 = 0.2mA Rx Charge Pump Polarity 0 = Normal Tx Charge Pump Polarity 0 = Normal Mixer Gain Control (Bit 1) Mixer Gain Control (Bit 2) Baseband Gain & RF Pad Cntrl (Bit 1) Baseband Gain & RF Pad Cntrl (Bit 2) Baseband Gain & RF Pad Cntrl (Bit 3) AFC Polarity 0 = Normal AFC Enable 0 = Disable Audio/Data Output Select 0 = Analog .com Test Mode (Bit 1) Test Mode (Bit 2) Test Mode (Bit 3) 1 = On 1 = On 1 = On 1 = 1.0mA 1 = 1.0mA 1 = Invert 1 = Invert t4U.com 1 = Invert 1 = Enable 1 = Digital DataShee TEST MODE 3 0 0 0 0 1 1 1 1 Test Bits 2 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 Test Mode I.D TeA TeB TeC TeD TeE TeF TeG Normal Mode Divider outputs at AUDO (digital) - Rx on Rxsynth out; Tx on Tx synth out; Rx + Tx on Ref synth out 6 poles of IF filter bypassed Demodulator test - Input at IF filter input via AFCC (47) pin, AFC disabled I Baseband output routed to AUDO (analog) Q Baseband output routed to AUDO (analog) nd 2 Mixer output routed to AUDO (analogue) IF filter test - input at IF filter input via AFCC, filter output routed to AUDO (analog); AFC disabled .com 16 DataSheet 4 U .com www..com PLL Data Register Contents - Cont. Gain Control - (Automatic / Manual) Gain switches to maximum following Load Enable (1) HIGH. The receive signal level is evaluated at intervals of 0.5ms and depending upon its signal level, the receiver gain is either unchanged, stepped up, or stepped down by one gain control increment, according to the table below. For example, if the channel is changed and the received signal is very strong then the change from maximum to minimum gain would take 7 x 0.5ms = 3.5ms. Auto Mode (Bit 3 = 1) Nominal RF Signal Level Increasing Decreasing < -86dBm > -80dBm < -76dBm > -70dBm < -66dBm > -60dBm < -56dBm > -50dBm < -46dBm > -40dBm < -36dBm > -30dBm < -26dBm > -20dBm RF section RF pad RF Mixer 0 15 0 15 0 5 0 5 0 -5 0 -5 -10 -5 -10 -20 Voltage Gain dB Baseband section st nd rd 1 Block 2 Block 3 Block 10 10 10 0 10 10 0 10 10 0 0 10 0 0 10 0 0 0 0 0 0 0 0 0 t4U.com DataShee Manual Mode (Bit 3 = 0) Mixer Gain Control 2 0 0 1 1 X X X X X X X X 1 0 1 0 1 X X X X X X X X Baseband Gain & RF Pad Control 3 X X X X 0 0 0 0 1 1 1 1 2 X X X X 0 0 1 1 0 0 1 1 1 X X X X 0 1 0 1 0 1 0 1 .com Voltage Gain dB RF section Baseband section st nd rd RF pad RF Mixer 1 Block 2 Block 3 Block -20 -5 5 15 -10 0 0 0 0 0 0 0 0 0 0 10 0 0 10 10 0 10 10 10 -10 10 10 10 -10 10 10 0 -10 10 0 0 .com 17 DataSheet 4 U .com www..com ELECTRICAL SPECIFICATIONS PARAMETER SYMBOL MIN TYP MAX OVERALL DEVICE: Power Supply Voltage Vdd 2.7 3 3.3 Operating Temperature Topr -20 65 Frequency of Operation Fin 902 928 SYSTEM LEVEL SPECIFICATIONS: (See applications circuit (Fig. 3) for additional details) Input Sensitivity (12db SINAD) -114 -115 Noise Figure ** NF 4.7 6.3 Input IP3 IIP3 -7.9 -6.9 Adj. Channel Rej.* (20dB SINAD) ACI 55 65 70 Out of Band Rejection 70 Tx Carrier Rejection 65 Receiver Bandwidth (-3dB) 110 120 130 RSSI (-116 to -66)** RSSI 0.2 2 RSSI Conversion Factor (Log) -25 -30 -35 Channel Spacing 150 Channel Step Size 50 L.O. Spurious Output -60 -57 Tx Output Power (At Antenna Input) Po -3 -0.5 1 Tx-Rx Frequency Bands 902.3-905.0 & 925.05-927.75 DEVICE LEVEL SPECIFICATIONS:** Noise Figure ** NF 8.5 9.2 .com Input IP3 IIP3 3.1 4 Input 1dB compression point ICP -25 -24 Desensitisation (5dB SINAD) -16 -15 I/Q Phase Imbalance (overall) 1 3 I/Q Amplitude Imbalance (overall) 0.5 1 Standby Current Istb 50 Rx Current Consumption (w/RF VCO) Idd(Rx) 25 Total Current Consumption (Rx+Tx) Idd(Total) 40 44 RECEIVER SECTION: (Device) PLL (Rx) Phase Noise (10kHz Offset) -85 -90 Spurious Products (Unwanted) -60 Step Size 50 Reference Frequency (External) 5 20 RF Quadrature Mixer Gain (Hi/Lo) *** Gv 24/14 25/15 26/16 Noise Figure NF 7.7 8.5 Input IP3 IIP3 6.1 6 Output 1dB compression point OCP -21 Amplitude Imbalance 0.5 Phase Imbalance 1 * 300kHz Channel Spacing ** RF Gain Control (High) *** Includes External Input Balun, (See Application Circuit, Figure (3)) UNITS V C MHz dBm dB dBm dB dB dB kHz Vdc mV/dB kHz kHz dBc dBm MHz dB dBm dBm dBm Deg. dB mA mA t4U.com DataShee dBc/Hz dBc kHz MHz dB dB dBm dBm dB Deg .com 18 DataSheet 4 U .com www..com ELECTRICAL SPECIFICATIONS - Cont. PARAMETER SYMBOL Buffer Amplifier Gain Gv Gain Gp Noise Figure NF Input IP3 IIP3 Output 1dB compression point OCP LPF1 Filter (Sallen-Key) Gain Gv, Gp Noise Figure NF Output 1dB compression point OCP Corner Frequency (-3dB) Filter Poles LPF2 Filter (Transconductance) Gain Gv, Gp Noise Figure NF Output 1dB compression point OCP Corner Frequency (-3dB) Filter Poles Variable Gain Amplifier / DC Offset Gain Range Gv, Gp Noise Figure NF .com Quadrature Mixer (Up-conversion) Gain Gv, Gp Noise Figure NF Amplitude Imbalance Phase Imbalance IF Bandpass Filter (BPF) Gain Gv, Gp Noise Figure NF Lower Corner Frequency (-3dB) Upper Corner Frequency (-3dB) Poles Audio Output Output Level (Std.Test Conditions) SINAD (-85dBm RF Level) SNR (-85dBm RF Level, +/-25kHz) Output Impedance (AUDOUT, Pin 13) Bandwidth (-3dB) Beat Note Level Automatic Frequency Control (AFC) Correction Range (+/-) Frequency Tolerance MIN 4.8 8.5 10.5 TYP 5 8.7 3.3 10.3 -17 12 4.9 -13 60 2 6 21 -19 70 6 40 11.8 MAX 5.2 9 3.8 UNITS dB dB dB dBm dBm dB dB dBm kHz 11.8 12.2 5.4 5 20 7 22 dB dB dBm kHz t4U.com 12.3 1.5 21 0.2 0.2 1 37 85 240 dB dB dB dBm dB Deg DataShee -1.5 19 0 20 0.1 -1 75 200 0 36 80 220 10 200 40 56 dB kHz kHz 170 230 2 0.3 -75 20 200 10 48 mVrms dB dB kohms kHz dBc kHz Hz 100 300 Maximum run length (digital mode) 1mS. High frequency audio response to be 72kHz in future version. .com 19 DataSheet 4 U .com www..com ELECTRICAL SPECIFICATIONS - Cont. PARAMETER SYMBOL MIN TRANSMIT SECTION: (Device) PLL (Tx) Phase Noise (10kHz Offset) -85 Phase Noise (100kHz Offset) -105 Phase Noise (1.0MHz Offset) -125 Phase Noise (22.75MHz Offset) -150 Spurious Products (Unwanted) -60 Step Size 50 Reference Frequency (External) 5 Power Amplifier (PA)** Power Output 0 Harmonic Level (2nd) Harmonic Level (3rd) Harmonic Level (4th) Transmit Audio Response Input Level (Standard Test Conditions) Bandwidth (-3dB)* 0.1 * Maximum run length (digital mode) 1mS. High frequency audio response to be 72kHz in future version. ** Includes External Output Balun, (See Applications Circuit, Figure (3)) TYP MAX UNITS -90 -108 -128 -155 20 1.5 -54.2 -44.2 -70.9 200 48 3 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc kHz MHz dBm dBc dBc dBc mVrms kHz t4U.com DataShee BOARD LAYOUT .com Designing ultra-high frequency (UHF) RF circuits requires careful attention to detail and layout. Careful attention to layout should be observed to minimize stray inductance and capacitance effects. This attention to detail will preserve RF sensitivity of the NT2903 CHIP-CEIVERTM. At high frequencies, microstrip or strip-line transmission line techniques must be employed. Using "state-of-the-art" CAD techniques for PCB layout, standard FR4 fiberglass PCB material (1.6-mm thickness) may be employed. For maximum performance, however, RF quality substrate material should be used. SUPPLY DECOUPLING Positive supply connections for the NT2903 are nominally 2.7V to 3.3V. All supply pins must be bypassed to an RF, Analog, or Digital ground plane depending upon the type of supply pin. For RF supply pins, a 100 pF ceramic capacitor in parallel with a 1.0 nF ceramic capacitor, both RF quality, should provide adequate decoupling. For analog and digital supply pins, 0.01-0.1F RF quality capacitors should be used. The bypass capacitors should be placed as close to all power supply pins as possible. An effort should be made to minimize the trace length between the capacitor leads and the respective NT2903 power supply and common pins. .com 20 DataSheet 4 U .com www..com GROUNDING The circuit designer should attempt to locate the NT2903 CHIP-CEIVERTM, associated analog input circuitry and interconnections as far as possible from logic circuitry. A solid RF analog ground should be placed around the LNA and associated RF filter circuitry, while a solid digital ground should be placed around the reference oscillator. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. Ground connections for the NT2903. Connect all ground pins together to a low impedance ground plane, as close to the device as possible. Observe proper RF grounding and shielding techniques. The NT2903 CHIP-CEIVERTM should be used with separate analog and digital ground planes. The digital and analog ground planes should be "summed" at one point, typically at the power supply filter capacitor. OPERATING PRECAUTIONS NUMA Technologies' plastic molded BiCMOS LSI devices are designed and manufactured for trouble-free operation when used under normal operating conditions. Our products are subjected to stringent electrostatic, mechanical strength, and environmental tests for assured reliability. When working with our products the user should observe the following precautions: t4U.com (1) Use the product in the range of the rated operating voltage, operating temperature, .com operating input/output voltage and input/output current. If the product is used outside these operating parameters, the user may experience high failure rates. Do not expose the product to excessive mechanical vibration, repetitive shock, or rapid or cyclic temperature changes. These factors can cause the bond wires in the plastic package to break. Although all terminals have electrostatic protection, damage may still occur if very high electrostatic potentials are applied. Use of a conductive container or aluminum foil for packaging and transportation is recommended. (Untreated plastic containers are NOT recommended.) Use grounded soldering tools and test equipment. The NT-2902 employs Electrostatic Discharge (ESD) protection. CMOS inputs shall be rated to 2Kv human body model / 1Kv charge contact model. Bipolar RF inputs shall be protected to the greatest extent possible and consistent with industry standards, while meeting RF performance parameters. DataShee (2) (3) (4) .com 21 DataSheet 4 U .com .com DataSheet 4 U .com www..com APPLICATION INFORMATION -- "900 MHz" Analog Cordless Telephone A circuit diagram for a high performance, cordless telephone transceiver is shown in Figure (3). This circuit is applicable to cordless phones compliant for use in the USA operating in the 902-928 MHz ISM band. The circuit will operate with a supply voltage of 2.7V to 3.3V. The "adjustment free" discriminator of the CHIP-CEIVERTM, along with the elimination of IF filters, provides a cost effective solution to cordless telephone applications. Tuning and power management functions for the NT2903 (U2) are accessed via an industry standard 3-wire compatible serial interface. The "printed" VCO inductors (L4, L5, L7, and L8) allow the transceiver to be tuned over the range of 902 to 928 MHz. An RF duplexer comprised of two dielectric resonant filters (FL1 and FL2) and a SAW filter (FL3) provide all of the required RF filtering. A low cost microprocessor with an analog-to-digital converter (A/D) input, can be used to measure the RSSI pin (36) of U2, which is proportional to the receive signal strength. t4U.com Figure (3), "900 MHz", High Performance, Cordless Telephone 22 .com DataShee www..com RECEIVER TEST SPECIFICATIONS: Standard Receiver Test Conditions: Unless otherwise specified, the standard receiver test conditions are: TA = 25C Fmod = 1kHz RF input carrier deviation = 25kHz peak Detected audio is C message weighted Interfering carrier deviation = 25kHz FMOD INT = 400Hz TxVCO On, locked, and modulated Sensitivity & Noise Figure: Given the worst case variation in the external blocks used in the receiver design, as shown in Fig. (3), the recovered audio SINAD shall be 12 dB @ RF input level of -114dBm. Typically, the 12dB SINAD is achieved at RF input level of -115dBm. Output Audio Level: t4U.com The nominal audio output level with 25kHz FM deviation shall be 200 mVrms. .com DataShee Dynamic Range: The Rx section of the NT2903 must maintain all aspects of specified operation from the lower RF input limit up to 0 dBm. (experience no significant change in the overall performance) There shall be no disruption in the Prescaler or the VCO operation (both Tx and Rx). Additionally, the device shall withstand input power levels of up to +5dBm at the NT2903 RF inputs (/RFI, RFI), without damage. The system SINAD and SNR resulting from an RF level being applied at 20dB above the minimum RF input level (required to produce 12dB SINAD) shall be maintained up to the maximum specified RF input level of 0 dBm. Also, the specified recovered audio output level at the audio output pin, AUDO (48) shall be maintained. Intermodulation: Given the worst case variations in the external circuit blocks, the input IP3 shall not be lower than -14 dBm. (this occurs using the typical Ceramic & SAW filter losses). The test (standard two tone test)conditions for this test are two equal level carriers placed on the 1st & 2nd adjacent channels to the desired test channel. For intermodulation test the 1st adjacent carrier is unmodulated but the 2nd adjacent is modulated with 400Hz tone & 25kHz deviation. .com 23 DataSheet 4 U .com www..com Spurious Response: a) Spurious Responses due to I/P signals > + 500kHz of the Channel Center Freq.: Spurious responses due to prescaler generated products which are modulated onto the LO should allow an interfering input signal to be at least 70 dB higher than the minimum RF carrier input level required to produce 25 dB SINAD. The resulting in-band spurious signal may be allowed to degrade the SINAD from 25 to 20dB. Receiver spurious response is also measured for various possible interfering frequencies and should allow an interfering input signal(e.g. 1/2 Tx LO+/-IF, 2 TxLO-RXLO +/-IF etc.) to be at least 70 dB higher than the minimum RF carrier input level required to produce 25 dB SINAD. The resulting in-band spurious signal may be allowed to degrade the SINAD from 25 to 20dB. b) Spurious Responses due to I/P signals +/- 325 to 500 kHz of the Channel Center Freq.: The receiver should allow an interfering input signal to be at least 60 dB higher than the minimum RF carrier input level required to produce 25 dB SINAD. The resulting in-band spurious signal may be allowed to degrade the SINAD from 25 to 20dB. c) Adjacent Channel: For the adjacent channel rejection measurement interfering carrier is applied at Fc one channel spacing. The receiver should allow an interfering adjacent channel input signal to be at least 55 dB higher than the minimum RF carrier input level required to produce 25 dB .com SINAD. The resulting adjacent channel signal may be allowed to degrade the SINAD from 25 to 20dB. d) Common Channel Suppression: Common channel suppression is used to express the ability of the receiver to discriminate against a modulated signal of the same frequency. The receiver common channel suppression should be greater than -12dB for analog modulated signals. The resulting co-channel signal may be allowed to degrade the SINAD from 25 to 20dB. Output match for the external SAW filter: The NT2903 shall present an input of match of 10dB or better over the pass band for the SAW filter output. The NT2903 receiver performance should not degrade due to an out-of-band impedance presented by the SAW filter at the RF inputs /RFI(33), RFI(34). Port Isolation: The Rx LO leakage at the RF input port shall be <-50dBm. Rx Spurious Emissions: The maximum level of any Rx spurious output shall be <-70dBm at the antenna. .com 24 t4U.com DataShee DataSheet 4 U .com www..com Transmitter Test Specifications: Spurious Outputs: The maximum spurious output levels at the antenna for the transmitter operating on both handset and base frequencies are shown below in Fig.(4) and Fig. (5) + 155KHz of Fc < 902.0 MHz -50 dBc 924.7 MHz >928 MHz -57dBc -57dBc -70dBc -95 dBm - 155KHz of Fc for Spurious 905.3 MHz -104 dBm for Noise above thermal in a 100KHz BW t4U.com DataShee Figure (4) - Base Transmitter Spurious Limits .com - 155KHz of Fc < 902.0 MHz 905.3 MHz 924.7 MHz -50 dBc >928 MHz -57dBc -57dBc -70dBc -95 dBm for Spurious -104 dBm for Noise above thermal in a 100 kHz BW + 155KHz of Fc Figure (5) - Handset Spurious Output Limits Any spurious signals produced by the device shall met FCC spurious emissions specifications, as specified under part 15, section 15.209 of the FCC rules, with reasonable margin. .com 25 DataSheet 4 U .com www..com Tx & Rx VCOs: Tx & Rx VCO's shall tune over a frequency range of 902-928 MHz and over the temperature range of -10 to 60C. The amplitude variation over the total tuning range should be less than 1dB.( 0.5dB) The maximum change in the VCO frequency in the locked state due to different loads (short/open) or when antenna is touched or brought near a metal object at the antenna input shall be 2.5 kHz. Tx Amplifier: Power level at the output of the amplifier shall be +1.5dBm with a variation in power level < 1.5 dB. (This includes the variations in amplitude from the VCO as well) Load Pull: The Tx amplifier should be stable (in-band) over VSWR of 10:1, the transmitter frequency change under the similar circumstances should not be more than 2.5kHz. Transmitter Test: t4U.com The transmitter modulation response and SINAD shall not change while the Rx receive levels vary from 0 to -116dBm. The transmitter performance shall also remain unaffected over the .com specified temperature range of -10 to 60C, TxVCO loop voltage, and when different loads are presented at the antenna. DataShee Device Test Specifications (NT2903) De-sensitization: Receiver de-sensitization shall be tested by applying an interferer, 500kHz from the receive carrier frequency, at the input of the device along with a desired signal. The desired signal shall be applied such that a reference SINAD of 25dB is achieved. Furthermore, an interferer shall be applied at a power level of -15dBm. The resultant SINAD shall not be less than 20dB, in the presence of the specified interferer. IIP3 Measurement: The Input IP3 for the device (NT2903) shall be tested by applying two (2) interfering signals at the input of the device along with a desired signal. The desired signal level at the input to the device shall be set at -77dBm. Given the desired signal level, the measured SINAD shall not exceed a reduction of 5dB from the reference SINAD of 25dB, in the presence of the specified interferers. The interferers shall have the following characteristics: T1 -25dBm, Fc+300kHz, Modulation = Off T2 -25dBm, Fc+600kHz, Modulation = 400Hz, 25kHz Deviation .com 26 DataSheet 4 U .com www..com Frequency Tables: This section outlines the frequencies and corresponding channel numbers used by the handset and base unit of both 900 MHz analog and digital phones. Handset: Channel 1 2 3 4 5 6 7 8 9 10 Transmit 925.05 925.35 925.65 925.95 926.25 926.55 926.85 927.15 927.45 927.75 Receive 902.3 902.6 902.9 903.2 903.5 903.8 904.1 904.4 904.7 905.0 Rx LO 1804.6 1805.2 1805.8 1806.4 1807.0 1807.6 1808.2 1808.8 1809.4 1810.0 Rx LO 1850.1 1850.7 1851.3 1851.9 1852.5 1853.1 1853.7 1854.3 1854.9 1855.5 Base: Channel 1 2 3 4 5 6 7 8 9 10 Transmit Receive 902.3 925.05 902.6 925.35 902.9 925.65 903.2 925.95 903.5 926.25 .com 903.8 926.55 904.1 926.85 904.4 927.15 904.7 927.45 905.0 927.75 t4U.com "CONFIDENTIAL: These materials contain confidential information proprietary to NUMA Technologies, Inc. Neither these materials nor information contained in same maybe disclosed by or used for benefit of any party without consent of NUMA Technologies, Inc." The information provided herein is believed to be reliable; however, NUMA Technologies assumes no responsibility for inaccuracies or omissions. NUMA Technologies assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Products mentioned in this document are covered under one or more of the following U.S. patents: 5,159,281, 5,239,273 and 5,272,448; Additional patents pending. Copyright 1998, 1999 NUMA Technologies CHIP-CEIVERTM is a trademark of NUMA Technologies, Inc. .com 27 DataSheet 4 U .com |
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